Keysight Technologies: Advanced Topics in Signal Integrity and Power Integrity
Thursday, September 28, 2023
Burlington Marriott
One Burlington Mall Road
Burlington, MA 01803
Agenda Timeline 9:30 a.m.- 3:00 p.m.
Registration Time 9:00 a.m.
Lunch Provided
What this event is about:
Join us to explore the latest innovations in Signal Integrity and Power Integrity in ADS 2023 (Update 1 & Update 2). We’ll first double-click into pathfinding for next-gen memory, and see how parallel simulations speed up circuit design. Next, you’ll see how PAM-3 is used in USB4 v2, how to ensure you are generating causal S-parameter models from your EM simulator, and how to simulate cascaded voltage regulators as a system.
9:10 a.m. |
Registration |
9:30 a.m. |
Memory: Advances in Memory System Design Workflow
- What's new in Memory Designer in the latest releases
- Advanced memory interface for pathfinding
- Latest simulation examples and demos
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10:30 a.m. |
Simulate with Confidence: Your Next Gen SerDes Design!
We will be discussing some of the latest SerDes standards that enable hyperscale computing.
- PCIe 6 & 5
- CXL 2
- USB4V2 (and USB4 Gen2 & 3)
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11:30 a.m. |
Lunch |
12:30 p.m. |
EM Modeling: Successful Extraction of High-Speed PCB Designs in Less Time
- How SIPro can help you successfully simulate your High-Speed PCB Designs
- Discussion on port setup, meshing and causality of extracted EM models
- Simulation workflow (Python script based) automation examples demonstrating increased productivity
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1:30 p.m. |
Expanding Power Integrity Simulations to Include Cascaded VRMs
- An iterative EM approach determines the average DC behavior, when dynamic regulators are cascaded in series.
- Steady-state behavior for an AC EM PCB model with cascaded dynamic switching regulators is solved using Harmonic Balance.
- Advanced conducted EMI simulations of cascaded VRM's help to analyze separate power rail noise vs. ground rail noise.
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2:30 p.m. |
Optional ADS Clinic & Afternoon Tea
Bring your laptop and your questions for the specialists!
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